(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the planarity and uniformity of interlevel dielectrics in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits having multiple conducting levels, planarization of the interlevel dielectric is most important. Typically, the interlevel dielectric is formed by depositing a silicon oxide layer over the surfaces of a conducting layer, coating on a spin-on-glass layer, and etching back the two layers to provide a planarized dielectric surface. FIG. 1 illustrates a partially completed integrated circuit device of the prior art. Semiconductor device structures, such as gate electrodes 14 and source and drain regions 16 have been formed in and on the surface of a semiconductor substrate 10. An insulating layer 18 is formed over the surface of the gate electrodes 14. A metal layer 20 is deposited over the insulating layer and patterned to form metal lines, as shown in FIG. 1. Now the interlevel dielectric layer is to be formed. A silicon oxide layer 22 is deposited conformally over the metal lines. Spin-on-glass layer 24 is coated over the silicon oxide surface.
Referring now to FIG. 2, the spin-on-glass layer 24 is etched back to planarize the layer and to expose the oxide on the tops of the metal lines. However, when the silicon oxide layer 22 is exposed to CHF.sub.3 /CF.sub.4 plasma during etchback, more oxygen atoms are released from their Si--O bondings. These oxygen atoms consume more CF.sub.2 atoms in the adjacent spin-on-glass material, thus enhancing the spin-on-glass etch rate. This is called the microloading effect. More spin-on-glass is consumed than expected. This results in degradation of the planarization, as shown in FIG. 2. The spin-on-glass surface is much lower than the oxide surface. The top layer of the interlevel dielectric sandwich is typically a tetraethoxysilane (TEOS) layer 26. The lack of planarization of the spin-on-glass layer 24 can cause the formation of a keyhole 28 in the TEOS layer for narrow metal spacing.
It is desirable to form a planarized interlevel dielectric layer without microloading effects and without keyhole defects.
U.S. Pat. No. 5,399,533 to Pramanik et al shows a method of eliminating microloading by replacing the oxide layer under the spin-on-glass layer with a nitride layer. U.S. Pat. No. 5,413,963 to Yen et al teaches planarizing the spin-on-glass layer by heating followed by a N.sub.2 treatment. U.S. Pat. No. 5,366,910 to Ha et al shows a method of forming a spin-on-glass layer which is treated with O.sub.2 plasma, then exposed to the atmosphere to increase the hydrogen content of the layer.